Power Optimized Programmable Embedded Controller

Power optimized programmable embedded controller

Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functionality. Clock-gating is the most common technique used for reducing processor’s power. In this work clock gating technique is applied to optimize the power of fully programmable Embedded Controller (PEC) employing RISC...

Optimized Fuzzy Controller Architecture for Field Programmable Gate Arrays

Optimized AES Rijndael implementation on embedded controller R8C

Advanced Encryption Standard (AES) Rijndael algorithm has gained popularity as it is deployed in various embedded systems. Realization of AES algorithm on microcontroller with minimum memory will be useful for deploying it in low cost applications. R8C microcontroller from Renesas is one of the popular microcontrollers in industrial application, being low cost and versatile processor having all...

optimized reversible programmable logic array (pla)

reversible logic circuits have found emerging attentions in nanotechnology,optical computing, quantum computing and low power design. a programmablelogic array (pla) is a universal circuit which is used to implement combinationallogic circuits. the main part of a pla is its and array. in this study we propose twotypes of optimized reversible programmable logic array (rpla) circuits. the firstty...

Flexible Circuits and Architectures for Ultralow Power A programmable gate array optimized for ultralow-power operation

| Subthreshold digital circuits minimize energy per operation and are thus ideal for ultralow-power (ULP) applications with low performance requirements. However, a large range of ULP applications continue to face performance constraints at certain times that exceed the capabilities of subthreshold operation. In this paper, we give two different examples to show that designing flexibility into ...